A buck converter consists of a power stage and a feedback control circuit. The power stage has a switching section and an output filter. The power stage switches an input node of the output filter between the power supply voltage source and the ground reference node. The output filter has an inductor between the input node and an output node with a capacitor connected between the output node and the ground reference node. The switching section in this example has a switch connected between the power supply voltage source and the input node of the output filter. A diode is connected between the input node of the output filter and the ground reference node. When the switch is activated, the current through the filter section flows from the power supply voltage source and when the switch is deactivated, the current flows from the ground reference node to the input of the filter section.
FIG. 1 is a schematic diagram of a buck converter of the related art having a continuous current mode (CCM) of operation. The power switching section 5 receives a set of clock pulses CLK that are generated at a fixed repetition rate. The clock pulses CLK are applied to the set input S of a set-reset latch RS1. The output Q of the set-reset latch RS1 is applied to the control terminal of the high side switch SH. A first terminal of the high side switch SH is connected to the input voltage source VIN and a second terminal of the high side switch SH is connected to an input terminal of the filter section 10. The input terminal is a first terminal of an inductor L1. When the clock pulses CLK as applied to the set input S of a set-reset latch RS1, triggers the set-reset latch RS1 such that the high side switch SH is closed such that a current from the input voltage source VIN flows to the first terminal of the inductor L1. The current IL flows through the inductor L1 and out the second terminal of the inductor L1. The second terminal of the inductor L1 is connected is to the first terminal of the capacitor COUT. The second terminal of the capacitor COUT is connected to the ground reference node. The current flowing in the inductor L1 flows into the capacitor COUT to charge the capacitor COUT and to bypass any alternating current and voltage variations to the ground reference node. The load current is a DC current passing to an external load. The output voltage VOUT is present at the junction of the second terminal of the inductor L1 and the first terminal of the output capacitor COUT.
It is known in the art, that the voltage (VL1) across the inductor L1 is determined by the formula:
      V          L      ⁢                          ⁢      1        =      L    ⁢                  ⅆ                  I          L                            ⅆ        t            The output voltage VOUT is equal to the difference of the power supply voltage source and the voltage VL1 across the inductor L1 in the on state. When the high side switch is opened, the slope of the current through the inductor L1 is the negative of the output voltage VOUT divided by the inductance of the inductor L1 (−VOUT/L1). The duty cycle of the current mode buck converter determines the on-state time and the off-state time. It can be shown that the output voltage VOUT is equal to the duty cycle D of the buck converter multiplied by the voltage level of the input voltage source VIN.
The feedback section 15 has two inputs. The first input is the output voltage VOUT at the first terminal of the output capacitor COUT and the second input is a sensing of the output current through the inductor L1. In some applications, the sensing of the output current IOUT is measured as a voltage across the equivalent series resistance of the inductor L1, a voltage across a small series resistor (not shown) placed in series with the inductor L1, or a voltage resulting from a magnetic coupling with an interconnection of the inductor L1 and the output capacitor COUT.
The first input of the feedback section 15 is applied to first input of an error amplifier OA1. A second input of the error amplifier OA1 receives a reference voltage level Vref. The output the error amplifier OA1 is an error voltage that is applied to a negative input of a comparator CP1. The inductor current IL sensor SENSIL senses the inductor current IL at the first terminal LX, transfers the sensed inductor current to the second input of the feedback section 15. The sensed inductor current is applied to the input of the resistor network RS to form the voltage VLX that is proportional to the voltage developed at the first terminal LX at the output of the resistor network RS. The voltage LX is a first input to a summation circuit 16. A compensation voltage is a second input to the summation circuit 16. The summation signal ILFB of the output of the summation circuit 16 is the second input to the comparator CP1. The output of the comparator CP1 is the stop signal STOP that is applied to the reset of the set-reset latch RS1. The output Q of the set-reset latch RS1 is a pulse width signal PWM that activates and deactivates the high side switch. When the error voltage VEA indicates that the output voltage VOUT is greater than the reference voltage level Vref, the comparator CP1 triggers the reset input R of the set-reset latch RS1 to deactivate the high side switch. The slope of the output current the reverses direction and the output current decreases at the slope determined by the magnitude of the output voltage VOUT and value of the inductor L1. At the next pulse of the clock pulses CLK, the high side switch is toggled in state to generate a saw tooth current wave for the inductor current IL. The output VEA of the error amplifier OA1 sets the target for the maximum or peak inductor current IL. The output VEA is regulated by the error amplifier OA1 to adjust the required peak inductor current IL to regulate the output voltage VOUT to a value proportional to reference voltage VREF.
When the high side switch SH is deactivated, it presents a high impedance from its first terminal to its second terminal. Since the current flowing in the inductor L1 cannot change instantaneously, the current is redirected from high side switch SH to the low side diode switch SL. Due to the positive inductor current, the voltage across the inductor L1 reverses polarity until low side diode switch SL becomes forward biased and begins conducting current. The voltage at the input terminal LX of the filter section becomes −(Vd) where the quantity Vd is the forward voltage drop of low side diode switch SL. The voltage present at the output terminal OUT of the filter section 10 is still the output voltage VOUT. The inductor current IL, now flows from the ground reference node through low side diode switch SL and to the output capacitor CL and to the output load. During the period that the high side switch SH is deactivated, the magnitude of the voltage applied across the inductor L1 is constant and equal to (VOUT+Vd+IL×RL). The voltage across the inductor L1 is negative causing the inductor current IL to decrease during the period that the high side switch SH is deactivated. Since the applied voltage is essentially constant, the inductor current IL decreases linearly.
FIG. 2 provides plots of the inductor current IL of the buck converter of FIG. 1 under high load, medium load, and light load conditions with only continuous conduction mode (CCM) of operation. At the rising edge of the clock pulse CLK at the time τ0, the set input S of the set-reset latch RS1 sets the output Q of the set-reset latch RS1 to activate the high side switch SH. The inductor current IL begins to rise from its minimum level at the time τ0. The inductor current IL increases until the voltage ILFB that is proportional to the filter current IL is greater than the error voltage VEA and the high side switch SH is deactivated at the time τ1. The inductor current IL then begins to decrease until the next rising edge of the clock pulse CLK. The change in the inductor current IL is essentially a ripple current that swings around the level of the high load current 20, the medium load current 25, and the low load current 30. Under the high load current 20, the inductor current IL does not have a level that is less than zero amps.
Under the medium load current 25, the inductor current IL is less than the level of zero amps between the points 27 and 29. At the time τ0, the set input S of the set-reset latch RS1 sets the output Q of the set-reset latch RS1 to activate the high side switch SH and the inductor current IL begins to increase. When the inductor current IL is less than the level of zero amps between the points 27 and 29, energy is lost from the system, because the energy is dissipated in the high side switch SH and the low side diode switch SL.
Under the light load current 30, the inductor current IL is less than the level of zero amps between the points 32 and 34. Again, at the time τ0, the set input S of the set-reset latch RS1 sets the output Q of the set-reset latch RS1 to activate the high side switch SH and the inductor current IL begins to increase. When the inductor current IL is less than the level of zero amps between the points 32 and 34, energy is again lost from the system, because the energy is dissipated in the high side switch SH and the low side diode switch SL. The inductor current IL in a buck converter operating in only a CCM shows a significant amount of negative inductor current that draws current from the capacitor CL at each clock cycle. This negative current causes Ohmic losses and shortens battery life in portable applications.
FIG. 3 is a schematic diagram of a buck converter of the related art having a continuous current mode (CCM) and discontinuous current mode (DCM) of operation. Since the losses from continuous current flowing in the continuous current mode (CCM) become significant at the low current load 30 of FIG. 2, a low side synchronous rectifier switch SR replaces the passive low side diode switch SL to prevent the negative current. The synchronous rectifier switch SR is often referred to as an active diode or a zero-crossing detector in many examples. In this instance of the buck converter, the high side switch SH and the synchronous rectifier switch SR are each formed of a metal oxide semiconductor (MOS) field effect transistor (FET) N1 and N2. In parallel with each of the MOS FET's N1 and N2 is a body diode DB1 and DB2 that are connected from the source to the drains of the MOSFET's N1 and N2. As is known in the art, the body diodes DB1 and DB2 are intrinsic diodes formed between the drain and the back-gate of the MOSFET's N1 and N2.
The input voltage source VIN is connected to the first electrode of the MOSFET N1 and the cathode of the body diode DB1. The second electrode of the MOSFET N1 and the anode of the body diode DB1 are connected to the first electrode of the MOSFET N2 and the cathode of the body diode DB2. The second electrode of the MOSFET N2 and the anode of the body diode DB2 are connected to the ground reference node.
The high side switch SH and the low side synchronous rectifier switch SR are controlled respectively by the high side driver output QH and a low side driver output QL of the switch control circuit 7. The gate of the MOSFET N1 is connected to the high side driver output QH and the gate of the MOSFET N2 is connected to the low side driver output QL. The switch control circuit 7 receives the CCM stop command 35 from the output of the comparator CP1 and the DCM Stop command 40 from the output of the zero crossing detector 17. A possible implementation of the zero crossing detector 17 is to determine when the voltage VLX at the input node LX of the inductor L1 in less than zero volts and the inductor current IL has crossed the zero amp level. When the clock pulses CLK arrive at the switch control circuit, the high side switch SH is activated to provide the inductor current from the input voltage source VIN through the first terminal to the second terminal of the high side switch SH. When the inductor current IL has reached the maximum level as indicated by the comparison of the summation signal ILFB from the output of the summation circuit 16 with the error voltage VEA, the comparator CP1 activates the CCM stop command 35 and the high side switch SH is deactivated. The low side synchronous rectifier switch SR is activated and the inductor current IL is then sourced from the ground reference node. The zero crossing detector 17 is activated when the voltage VLX at the input node LX of the inductor L1 becomes less than zero volts. When the inductor current IL becomes less than zero, the zero crossing detector 17 activates the DCM stop command 40 and the low side synchronous rectifier switch SR is deactivated. Both the high side switch SH and the low side synchronous rectifier switch SR are now deactivated. The inductor current IL will then remain at zero amps.
FIG. 4 provides plots of the inductor current IL of the buck converter of FIG. 3 under high load, medium load, and light load conditions with continuous conduction mode (CCM) and discontinuous conduction mode (DCM) of operation emulating ideal diode rectification. Refer first to the high load current 20 situation. At the rising edge of the clock pulse CLK at the time τ0, the rising edge of the clock CLK applied to the input of the switch control circuit 7 within the switching section 5 causes the high side driver output Q to activate the high side switch SH. The inductor current IL begins to rise from its minimum level at the time τ0. The inductor current IL increases until the voltage ILFB that is proportional to the filter current IL is greater than the error voltage VEA at the time τ1. The inductor current IL then begins to decrease until the next rising edge of the clock pulse CLK. The change in the inductor current IL is essentially a ripple current that swings around the level of the high load current 20, the medium load current 25, and the low load current 30. Under the high load current 20, the inductor current IL does not have a level that is less than zero amps and is operating in the continuous current mode.
Refer now to the medium load current 25 situation. As before the inductor current IL begins to rise from its minimum level at the time τ0. The inductor current IL increases until the voltage ILFB that is proportional to the filter current IL is greater than the error voltage VEA at the time τ2. The inductor current IL then begins to decrease until the zero crossing detector 17 determines that the voltage VLX at the input node LX of the inductor L1 is greater than the zero volts at the time τ3. The zero crossing detector activates the DCM stop command 40 and the switch control circuit 7 sets the low side driver output QL to deactivate the low side synchronous rectifier switch SR. In ideal diode operation, the inductor current IL will remain at nearly zero amps until the next cycle start at time τ0.
Refer now to the light load current 30 situation. As before the inductor current IL begins to rise from its minimum level at the time τ0. The inductor current IL increases until the voltage ILFB that is proportional to the filter current IL is greater than the error voltage VEA at the time 4. The inductor current IL then begins to decrease until the zero crossing detector 17 determines that the inductor voltage VLX at the input node LX of the inductor L1 is greater than zero at the time τ5. The zero crossing detector activates the DCM stop command 40 and the switch control circuit 7 sets the low side driver output QL to deactivate the low side synchronous rectifier switch SR. In ideal diode operation, the inductor current IL will remain at nearly zero amps until the next cycle start at time τ0.
FIG. 5 provides plots of the inductor current IL and the voltage VLX at the input node LX of the inductor L1 of the buck converter of FIG. 3 under medium load conditions with continuous conduction mode (CCM) and discontinuous conduction mode (DCM) of operation emulating non ideal diode rectification. The zero crossing detector 17 is implemented using a comparator that will compare the voltage VLX at the input node LX of the inductor L1 with a defined reference voltage VREF2. As in FIG. 4 for the medium load current 25 situation, the inductor current IL begins to rise from its minimum level at the time τ0 at the rising edge of the clock CLK. The high side switch SH is turned on and the low side synchronous rectifier switch SR is turned off, thus magnetizing the inductor L1. The inductor current IL increases until the voltage ILFB that is proportional to the filter current IL is greater than the error voltage VEA at the time τ1. The inductor current IL then begins to decrease, as the inductor L1 demagnetizes with the high side switch SH deactivated and the low side synchronous rectifier switch SR is turned on. At the time τ1, the voltage VLX at the input node LX of the inductor L1 becomes positive and activates the zero crossing detector 17. The zero crossing detector 17 monitors the inductor current IL to determine when it has approached approximately zero amps. The zero crossing detector 17 activates the DCM stop command 40 and the switch control circuit 7 sets the low side driver output QL to deactivate the low side synchronous rectifier switch SR at the time τ2. The inductor current IL continues to flow as shown between time τ2 and time τ3. During the period between time τ2 and time τ3, the voltage VLX is held less than zero volts. At the time τ3, the inductor current IL becomes approximately the zero volt level and the voltage VLX is set to the output voltage VOUT. The inductor current IL will remain at nearly zero amps until the next cycle start at time τ4.
At the next cycle start at time τ4, the inductor current IL begins to rise from its minimum level until the time τ5. The inductor current IL then begins to decrease, as the inductor L1 demagnetizes with the high side switch SH deactivated and the low side synchronous rectifier switch SR is turned on. At the time τ5, the voltage VLX at the input node LX of the inductor L1 becomes greater than zero volts to activate the zero crossing detector 17. The zero crossing detector 17 monitors the inductor current IL to determine when it has approached approximately zero amps, at the time τ6. The zero crossing detector 17 activates the DCM stop command 40 and the switch control circuit 7 sets the low side driver output QL to deactivate the low side synchronous rectifier switch SR at the time τ6. The inductor current IL continues to flow as shown between time τ6 and time τ7. During the period between time τ6 and time τ7, the voltage VLX is held at approximately zero volts and the inductor current IL continues decrease below zero amps to the time τ7. At the time τ7, the inductor current IL begins to rise to zero amps at the time τ8. Between the time τ7 and time τ8, the voltage VLX rises to the level somewhat above the input voltage VIN due to the voltage drop across the body diode DB1. At the time τ8, the inductor current IL is approximately the zero volt level and the voltage VLX is set to the output voltage VOUT between the time τ8 and the time τ9.
In this example, the cycle between the time τ9 and the time τ14 is identical to that of the cycle between the time τ4 and the time τ9. Similarly, the cycle between the time τ14 and the time τ17 is identical to that of the cycle between the time τ0 and the time τ3. Between the time τ2 and time τ4, the inductor current IL was still slightly positive when the low side synchronous rectifier switch SR is deactivated. The inductor L1 behaves as a current source for the inductor current IL and the inductor current IL flows through the body diode DB2. The voltage VLX thus is set to the voltage level of approximately −0.7V. Alternately, between the time τ6 and time τ8, the inductor current IL was still slightly negative when the low side synchronous rectifier switch SR is deactivated. The inductor L1 behaves as a current source for the inductor current IL and the inductor current IL flows through the body diode DB1. The inductor current is injected toward the input node LX of the inductor L1 thus forcing the voltage VLX to be set to approximately to the input voltage VIN plus +0.7V (VIN+0.7V).